Design of Cost Efficient Noise Tolerant Digital VLSI Circuits based on Probabilistic methods

Noise in digital logic circuits does not reduce with the scaling down of CMOS devices. The conventional CMOS design does not provide noise immunity when the circuits are operated in the sub threshold region. In order to enhance the performance of the circuit and to handle the errors caused due to noise that are random and dynamic in nature, a cost effective probabilistic based noise tolerant circuit design is proposed. The idea is based on master-slave Markov Random Field (MRF) mapping and master-slave MRF logic gate design. To illustrate this concept, simulations have been carried out for a simple NAND gate and later the same idea is implemented in an 8 bit Carry Look Ahead (CLA) Adder. This methodology trades hardware cost for circuit accuracy. The proposed technique offers better noise immunity and tolerance in comparison with the conventional CMOS design. Also, the power consumption is expected to be lesser with increased accuracy and reduced output degradation. Finally, the transistor count is expected to be reduced considerably in comparison with the direct MRF mapping technique. Keywords— MRF technique, sub threshold region, probabilistic based,CLA, noise tolerant, master and slave. __________________________________________________*****_________________________________________________